This invention relates to a cache system and, in particular, to a cache system formed on a plurality of buses connected via a bus bridge and hierarchically arranged.
In order to expand a shared-memory multiprocessor system, it has been proposed to connect a plurality of system buses via a bus bridge. A number of such multiprocessor system with an improved expandibility are known in the art.
For example, Japanese Unexamined Patent Publication (JP-A) No. 297642/1996 discloses a shared-memory multiprocessor system in which two system buses are connected via a sort of a bus bridge called a directory. The publication also discloses a technique to guarantee cache coherency over store-in-caches.
In the above-mentioned system, the two system buses connected via the directory have bus cycles synchronized with each other with the offset of a half cycle. Upon detection of competing requests from these buses to the same request address, the request later issued is canceled while the preceding request is preferentially transferred to the system bus. Thus, the cache coherency is maintained upon occurrence of competing write requests between the system buses.
For read requests, data are essentially acquired from a main memory except when "dirty" data incoincident with data in the main memory are acquired from another cache. Therefore, even if "clean" data coincident with the data in the main memory are present in the same bus, the data must be acquired via the bus bridge from the main memory connected to the other system bus.
On the other hand, Japanese Unexamined Patent Publication (JP-A) No. 110844/1994 discloses a distributed shared memory multiprocessor system in which an internal bus connected to a CPU cache memory and a main memory is connected to a shared bus via a bus bridge called a sharing control section.
The sharing control section comprises a cache state tag memory memorizing the state of the cache memory connected thereto. Upon executing a write operation, the sharing control section refers to the content of the tag memory. If a data block is in a shared state, an invalidate instruction is delivered through the shared bus to other sharing control sections. Thus, the cache coherency is maintained.
The above-mentioned conventional cache systems are disadvantageous in the following respects.
As a first disadvantage, it is impossible to avoid write confliction if the multiprocessor system includes three or more system buses connected to one another.
Specifically, in the shared memory multiprocessor system disclosed in Japanese Unexamined Patent Publication (JP-A) No. 297642/1996, it is impossible to guarantee the cache coherency when store operations are simultaneously performed in caches connected to the system buses at opposite ends among the three system buses connected to one another.
In the distributed shared memory multiprocessor system disclosed in Japanese Unexamined Patent Publication (JP-A) No. 110844/1994, reference is made to the cache state tag memory in the sharing control section upon executing the write operation and the invalidate instruction is sent to the shared bus depending on the content of the cache state tag memory. However, no disclosure is made about how to maintain the cache coherency upon occurrence of competing invalidate instructions on the shared bus.
As a second disadvantage, the data must be acquired from the main memory in case where the clean data coincident with the data in the main memory is to be acquired. This will adversely affect the performance.
If a cache holding the clean data is present at a location nearer from a data requesting source than the main memory, the above-mentioned disadvantage can be removed by acquiring the data from the cache. In this event, however, another problem will arise. Specifically, the bus bridge must have an exact copy of a cache tag. Alternatively, a read request delivered on one system bus must not be forwarded to the other system bus until a result of lookup of the cache is given.